Embodiments of the invention relate generally to integrated circuit packages and, more particularly, to wafer level packages for integrated circuits. Wafer level packages are manufactured using laminated re-distribution layers and high density interconnects.
As integrated circuits become increasingly smaller and yield better operating performance, packaging technology for integrated circuit (IC) packaging has correspondingly evolved from leaded packaging to laminated-based ball grid array (BGA) packaging and eventually to chip scale packaging (CSP). Advancements in IC chip packaging technology are driven by ever-increasing needs for achieving better performance, greater miniaturization and higher reliability. New packaging technology has to further provide for the possibilities of batch production for the purpose of large-scale manufacturing thereby allowing economy of scale.
One specific form of CSP is wafer level packaging (WLP). WLP adopts an area-array packaging approach that is utilized in BGA packaging. This approach enables WLP to have a packaging outline that is substantially identical in size to the IC chip, making WLP the smallest form of CSP. WLP allows the IC packaging process to be carried out at wafer level as well as incorporate wafer level reliability and facilitate IC burn-in tests. Wafer level packaging has therefore attracted immense interest in the electronics industry for being a potential solution in IC packaging process that can provide low-cost production through large-scale manufacturing.
One current WLP manufacturing method is “Re-distribution Layer and Bump” manufacturing. In Re-distribution Layer and Bump manufacturing, a multi-layer thin-film metal rerouting and interconnection system is deposited to each device on the wafer. This additional level of interconnection redistributes the peripheral bonding pads of each chip to an area array of underbump metal pads that are evenly deployed over the chip's surface. The solder balls or bumps used in connecting the device to the application circuit board are subsequently placed over these underbump metal pads.
Application of the rerouting and interconnection system is typically achieved using the standard photolithography and thin film deposition techniques employed in the device fabrication itself. That is, a spin-on deposition technique is typically used to deposit a benzocyclobutene (BCB) or polyimide material and form the re-distribution layers. Deposition of the re-distribution layers via a spin-on application process, however, has inherent limitations in regards to the structure and functionality of the resulting WLP that is produced. For example, the formation of spin-on layers on the silicon wafer imparts stress to the silicon wafer, which can result in wafer warpage. To minimize wafer warpage, the number of spin-on layers must be limited to 1 or 2 layers and/or a thicker die than what is preferable must be employed. Also, high temperatures are required to cure spin-on dielectrics, which may not be compatible with all metallurgies. Furthermore, spin-on layers only allow for the redistribution/re-routing of the peripheral bonding pads and do not allow for the incorporation of addition elements into the WLP, such as embedded resistors/capacitors, shielding layers or other micro-electromechanical systems (MEMS).
The stress induced on the silicon wafer also imposes limitations on formation of an input/output (I/O) system on the WLP. That is, because of the stress imparted on the silicon wafer by the spin-on layers, larger and more robust bumps (i.e., solder balls/connections) and an underfill epoxy are needed for formation of the I/O system interconnection. Use of these large solder balls and the underfill epoxy limits the bump density of the I/O system and limits the level of miniaturization of the WLP that is achievable.
Accordingly there is a need for a method for WLP fabrication that allows for the application of multiple re-distribution layers while minimizing stress and warpage of the wafer die. There is a further need for a fabrication method that reduces solder ball/bump pitch and height to allow for greater density in the I/O system interconnect and miniaturization of the WLP.